Randomization

The transmitted bitstream must contain frequent transitions between 0 and 1 so that the receiver's clock recovery circuit can stay synchronized to the signal. The receiver has no independent clock; it infers the sender's bit timing from the transitions in the incoming signal. A phase-locked loop (PLL) tracks these transitions and adjusts its internal clock to stay aligned. If the data happens to contain long runs of the same bit (e.g. a block of zeros), there are no transitions and the PLL drifts, causing the receiver to misinterpret subsequent bits.

Randomization prevents this by XOR-ing the frame data with a deterministic pseudo-random sequence generated by a linear feedback shift register (LFSR) — a simple shift register whose input bit is a function of its current state, producing a sequence that appears random but is entirely predictable. The same sequence is known to both sender and receiver. Because XOR is its own inverse (applying it twice returns the original value), the receiver applies the identical operation to recover the original data.

CCSDS defines three randomizer variants. The TC randomizer uses a 255-byte sequence generated by the polynomial $x^8 + x^6 + x^4 + x^3 + x^2 + x + 1$. The TM randomizer uses the polynomial $x^8 + x^7 + x^5 + x^3 + 1$, available in a 255-byte (legacy) or 131071-byte (recommended) variant. The longer sequence is preferred because it avoids correlation with periodic frame content.

Randomization is always applied first, before FEC encoding, because the FEC parity symbols are computed over the randomized data and therefore do not need separate randomization.